The present invention relates generally to multilevel quantizers, particularly two-phase multilevel quantizers designed to be implemented in reduced amounts of chip area and also designed to dissipate reduced amounts of power. The invention also relates more particularly to high-performance, low-power delta-sigma modulators and delta sigma analog-to-digital converters (ADCs) which include such two-stage multilevel quantizers.
The closest prior art is believed to be represented by the article “A 3-mW 74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC With a Tracking ADC Quantizer in 0.13-μm CMOS” by Lukas Dörrer et al., IEEE Journal of Solid-State Circuits, Volume 40, Number 12, December 2005, pages 2416-2427. This reference discloses a third-order continuous-time 4-bit delta-sigma ADC, and also discloses reduction of power consumption by using a tracking ADC. The foregoing reference does not disclose interpolation of the quantizer output, and suffers from several major shortcomings. One shortcoming is that the disclosed delta-sigma ADC requires a separate circuit to set up the initial modulator DC operational point. It also requires additional digital to analog converter (DAC) circuits, and suffers from potential modulator instability due to parasitic high frequency input signal leakages and the like. The foregoing reference discloses the common technique of using a simplified first order dynamic element matching (DEM) circuit, but that is insufficient to overcome the above mentioned shortcomings.
FIG. 1 shows a typical multibit delta-sigma modulator 1, which includes a summing element 3 that sums an input signal Vin with a negative feedback signal on conductor 4 and applies the summation result via conductor 5 to the input of a linear loop filter 6. The output 7 of loop filter 6 is applied to the input of a conventional multilevel quantizer 8. The output 9 of multilevel quantizer 8 is applied to the input of a DEM circuit 10. There are several well known DEM circuit topologies which could be used for DEM circuit 10, which functions to remove the effect of mismatch between feedback elements of feedback DAC 12. The output conductors 11 of DEM circuit 10 are coupled to the input of DAC 12, the output of which produces the above mentioned negative feedback signal on conductor 4.
FIG. 2 illustrates a typical flash ADC-based quantizer implementation of multilevel quantizer 8 of FIG. 1. Multilevel quantizer 8 includes, for example, a resistor string 15 which includes 16 equal resistors R-0,1,2 . . . 15 connected in series. Tap points 16-0,1 . . . 15 are connected to the (−) inputs of 16 comparators 17-0,1 . . . 15 as shown. The (+) inputs of comparators 17-0,1 . . . 15 are connected to an input signal VQin produced by loop filter 6. Typically, multilevel quantizer 8 operates according to a thermometer code, and produces output voltages designated as Levels 0,1,2 . . . 15 on comparator output conductors 9-0,1,2 . . . 15, respectively, as the input signal VQin is increased from ground voltage to Vref volts. The corresponding thermometer code values, Levels 0,1,2 . . . 15, are applied to the inputs of DEM circuit 10.
Multilevel delta-sigma modulator topology is becoming more common because it further reduces quantization noise and because it relaxes certain analog circuit design constraints, such operational amplifier slew requirements and bandwidth requirements of the first integrator stage in the loop filter.
Since a delta-sigma modulator is a feedback system, the quantizer 8 needs to introduce a minimum delay to ensure stability of the system. This minimum delay requirement seriously limits the practical options for the topology of the multilevel quantizer. Flash type ADCs are normally used as quantizers due to their low latency, which refers to time delay between the outputs and inputs thereof. However, it is well-known that flash ADCs are characterized by low efficiency and low resolution. Compared with other ADCs, such as SAR or pipeline ADCs, a flash ADC consumes more power and requires more die area, even though the latency of a flash ADC is lower than the other types. Although increasing quantizer resolution/quantizer levels inside multilevel delta-sigma ADCs reduces output swings (and hence also the power consumption) of the integrators, reduces quantization noise, and decreases performance sensitivity to clock jitter, the low efficiency of conventional flash-based quantizer designs results in excessive power consumption and excessive die area and therefore diminishes the advantages of increased quantizer resolution/quantizer levels of the conventional flash-based quantizers. Conventional flash type quantizers of the type shown in FIG. 2 are considered to be very inefficient and not suitable for many future converter designs.
Thus, there is an unmet need for an improved multilevel quantizer topology which can be implemented in a substantially reduced amount of chip area and which consumes substantially less power than conventional multilevel quantizers, and also provides the advantage of small internal integrator output signal swings.
There also is an unmet need for an improved ADC which can be implemented in a substantially reduced amount of chip area and which consumes substantially less power than ADCs including conventional multilevel quantizers, and also provides the advantage of a small internal signal swing.
There also is an unmet need for an improved quantizer topology which requires simpler control logic circuitry, consumes much lower power, and requires less die area than the prior art flash-based quantizer designs.